1. Field of the Invention
The present invention relates to providing redundancy for programmable memory elements in a field programmable gate array (FPGA). More particularly, the present invention relates to providing redundancy for floating trap configuration memory elements in an FPGA.
2. The Background Art
Programmable logic devices (PLDs) are integrated circuit devices which contain gates or other general-purpose cells whose interconnections can be configured by programming to implement nearly any desired combinatorial or sequential function. Field programmable gate arrays (FPGAs) are well known in the PLD art. FPGAs generally include an array of general-purpose logic circuits, typically referred to as logic blocks, which can be programmed by programmable elements to implement virtually any logic function. The programmed logic elements in the gate array are connected together by routing resources to form a desired integrated circuit. The routing resources are connected to each other and to the logic elements in the gate array by programmable elements.
It is well known in the art that both volatile and non-volatile programmable elements have been used in FPGA devices. Volatile programmable elements are often a pass transistor controlled by a static random access memory (SRAM) cell. In an SRAM based reprogrammable FPGA, the programmable elements are typically passgates controlled by information stored in an SRAM configuration memory. Nonvolatile programmable elements include antifuses and floating gate transistors. In an antifuse based FPGA, the antifuses are programmable elements that represent an open state until programmed. The antifuses are disposed to provide the interconnections among the routing resources and to program the programmable logic elements.
In a floating gate transistor based FPGA, the floating gate element typically is the switching element employed to provide the interconnections among the routing resources and the programmable logic elements. Some examples of floating gate based FPGA devices are disclosed in U.S. Pat. Nos. 6,356,478; 5,764,096; 6,252,273; and 5,838,040. These devices employ floating gates similar to those used in flash memories, but adapted for use in programmable arrays. In addition to being non-volatile, configuration in a floating gate based device does not require as much integrated circuit area as configuration in an SRAM based device. Programmable antifuse based architectures and reprogrammable SRAM and floating gate memory cell based architectures are well known in the FPGA art.
Generally, in a floating gate memory cell, an MOS based transistor has an additional unconnected or floating polysilicon layer disposed in a dielectric between a semiconductor surface and the gate of the MOS transistor. To program the floating gate memory cell, electrons are placed on the floating polysilicon layer, and to erase the floating gate memory cell, electrons are removed from the floating polysilicon layer. As is well known in the art, a floating gate memory cell is programmed when sufficient electrons are placed on the floating polysilicon layer to prevent the MOS transistor of the floating gate memory cell from being turned on. The charged floating polysilicon layer opposes a voltage which, when applied to the gate of the floating gate memory cell would typically turn-on the MOS transistor of the floating gate memory cell. When these electrons are removed, a normal operating voltage applied to the gate of floating gate transistor will result in current flowing through the MOS transistor of the floating gate memory cell. This current may then be sensed to determine whether a particular floating gate memory cell has been programmed.
There are a variety of known floating gate memory cell technologies. These differences in the art are due at least in some instances to the specific geometry of the floating gate, the distance from the semiconductor surface of the floating gate in the dielectric, the inclusion of additional gates in the MOS transistor of the floating gate memory cell, the manner in which electrons are placed on and removed from the floating gate, and the diverse arrangements of the floating gate memory cells into memory cell arrays. These various technologies, well known to those of ordinary skill in the art include at least, electrically programmable read only memory (EPROM), electrically erasable and programmable read only memory (EEPROM), flash EEPROM, NOR flash and NAND flash.
An EPROM memory cell can be programmed by channel hot electron injection. For channel hot electron injection, well known to those of ordinary skill in the art, in a substrate ground mode with the substrate held at 0 volts, the gate of the MOS transistor in the floating gate memory cell is held at about 9 to about 12 volts, the source of the MOS transistor in the floating gate memory cell is held at 0 volts, and the drain of the MOS transistor in the floating gate memory cell is held at about 4 to about 5 volts. In a substrate enhanced mode with the substrate held at −2 to about −4 volts, the gate of the MOS transistor in the floating gate memory cell is held at about 6 to about 8 volts, the source of the MOS transistor in the floating gate memory cell is held at 0 volts, and the drain of the MOS transistor in the floating gate memory cell is held at about 3 to about 4 volts. The electric field generated by the voltage between the gate and the source provides enough energy to some of the electrons traveling from source to the drain to collect on the floating gate. The programming time for channel hot electron injection is about 1 ms to about 5 ms. An EPROM memory cell is erased by UV light.
An EEPROM memory cell is either programmed by channel hot electron injection or Fowler-Nordheim tunneling. With Fowler-Nordheim tunneling, well known to those of ordinary skill in the art, in a substrate ground mode with the substrate held at 0 volts, the gate of the MOS transistor in the floating gate memory cell is held at about 12 to about 15 volts, and the source and the drain of the MOS transistor in the floating gate memory cell is held at 0 volts. In a substrate enhanced mode with the substrate held at about 6 to about 8 volts, the gate of the MOS transistor in the floating gate memory cell is held at about −6 to about −8 volts, and the source and the drain of the MOS transistor in the floating gate memory cell is held at 0 volts. This results in electrons tunneling onto the floating gate.
In Fowler-Nordheim tunneling erase of an EEPROM memory cell, well known to those of ordinary skill in the art, in a substrate ground mode with the substrate held at 0 volts, the gate of the MOS transistor in the floating gate memory cell is held at about −12 to about −15 volts, and the source and the drain of the MOS transistor in the floating gate memory cell is held at 0 volts. In a substrate enhanced mode with the substrate held at about −6 to about −8 volts, the gate of the MOS transistor in the floating gate memory cell is held at about 6 to about 8 volts, and the source and the drain of the MOS transistor in the floating gate memory cell are held at 0 volts. This results in electrons tunneling off of the floating gate. The programming and erase times for Fowler-Nordheim tunneling are about 2 ms to about 20 ms.
A flash EEPROM memory array is quite similar to an EEPROM memory array, with the notable difference that a flash EEPROM can be erased on a block level basis. The erase becomes a part of the program routine, and the data to be programmed is typically stored in an on-chip buffer.
A NOR flash memory array is typically programmed by channel hot electron injection, and erased by Fowler-Nordheim tunneling. A NAND flash is programmed and erased by Fowler-Nordheim tunneling. In the programming and erase of a NAND flash the bias is applied between the gate and the substrate of the MOS transistor in the floating gate memory cell and is typically greater than 20 volts. “NOR” and “NAND” flash are referred to as such based upon the manner in which the memory cells in the flash memory cell arrays are connected to each other.
Floating gate memory cells have some performance characteristics such as long programming and erase times, high programming voltages, insufficient data retention times, limited number of programming cycles, and large integrated circuit area requirements which have led to the investigation and development of other programmable non-volatile memory (NVM) technologies.
One of these technologies is a floating trap MOS transistor. In a floating trap MOS transistor, charge is stored (trapped) in or removed from after being trapped in, a dielectric separating a gate of a MOS transistor from the semiconductor substrate. Unlike a floating gate transistor, where charge stored on the polysilicon conductor may flow freely in the polysilicon conductor, charge stored in a floating trap MOS transistor remains in the region of the floating trap material above the source or drain where it was originally placed during programming. Accordingly, a bit of information may be stored above each of the junctions of a floating trap MOS transistor for a total of two bits.
Two well known, and similar floating trap transistor technologies include silicon-oxide-nitride-oxide-silicon (SONOS) and metal-oxide-nitride-oxide-silicon (MONOS). In each of these devices, the dielectric separating the gate of the MOS transistor from the semiconductor substrate is an oxide-nitride-oxide (ONO) layer. The programming of MONOS/SONOS devices has been by both channel hot electron injection and Fowler-Nordheim tunneling as described above. After programming, the charge is trapped in the nitride layer in the region of the floating trap material above the source or drain of the MOS transistor of the MONOS/SONOS device. In more recent advances in the floating trap transistor technology of MONOS/SONOS devices, a thicker bottom oxide layer in the ONO dielectric has been employed to improve charge retention and to reduce read disturb.
Erase of MONOS/SONOS devices has been by both Fowler-Nordheim tunneling, as described above, and tunneling enhanced hot hole injection. In erase by tunneling enhanced hot hole injection, well known to those of ordinary skill in the art, the charge stored in either one or both of the regions of the floating trap material above the source or drain of the MOS transistor of the MONOS/SONOS device may be erased by injecting holes into the desired charge trapping region of the nitride layer. In a one sided substrate ground mode with the substrate held at 0 volts, the area above the drain junction can be erased by applying about −6 to about −8 volts to the gate of the MOS transistor in the floating gate memory cell, letting the source of the MOS transistor in the floating gate memory cell float, and applying about 4 to about 7 volts to the drain of the MOS transistor in the floating gate memory cell. In a two-sided substrate ground mode, both the source and the drain are held at about 5 to about 6 volts.
In a one sided substrate enhanced mode with the substrate held at −2 to about −3 volts, the area above the drain junction can be erased by applying about −4 to about −6 volts to the gate of the MOS transistor in the floating gate memory cell, letting the source of the MOS transistor in the floating gate memory cell float, and applying about 3 to about 4 volts to the drain of the MOS transistor in the floating gate memory cell. In a two-sided substrate enhanced mode, both the source and the drain are held at about 3 to about 4 volts.
To read the charge trapped above a first junction in a MONOS/SONOS device with the substrate at ground, a first potential about 1 to about 2 volts is applied to a first source/drain region associated with the first junction, a second potential at ground is applied to a second source/drain associated with a second junction in the MOS transistor of the MONOS/SONOS device, and a third potential of about 3 to about 4 volts is applied to the gate of the MONOS/SONOS device. During the read, a sense of the current through the MONOS/SONOS device is performed to determine the programmed state of the floating trap device. It should be appreciated that the ratio of the potential differences between the first potential and the second potential and the third potential and the second potential is about 1.5 to about 4.
In U.S. Pat. No. 5,768,192 a charge trapping device is described that is programmed using channel hot electron injection, and erased with tunneling enhanced hot hole injection. To read the charge trapped above a first junction in a MONOS/SONOS device with the substrate at ground, a first potential at ground is applied to the first source/drain region associated with a the first junction, a second potential at about 1 to about 2 volts is applied to a second source/drain associated with a second junction in the MOS transistor of the MONOS/SONOS device, and a third potential at about 3 to about 4 volts is applied to the gate of the MONOS/SONOS device. It should be appreciated that the ratio of the potential differences between the second potential and the first potential and the third potential and the first potential is about 1.5 to about 4.
In a PLD, when during manufacturing a defect occurs in either the logic or programmable elements, it is desirable to have redundancy in the PLD to avoid the defect, and thereby keep the entire device from being defective. A proposed scheme for providing redundancy in a PLD when either the logic elements or the programmable elements for connecting the logic elements together have a defect is described in U.S. Pat. No. 5,498,975 to Cliff et al. In this scheme, spare columns or rows of logic blocks and programmable elements (switches) are provided in the PLD array to replace the defective logic elements or programmable elements in the PLD. These additional columns or rows are provided at the expense of reducing the available logic resources in the PLD. Accordingly, it would advantageous to provide redundancy in a PLD without including spare rows or columns in the PLD.